By David Powell
The layout of desktops to be embedded in serious real-time purposes is a posh job. Such platforms must never in simple terms warrantly to satisfy not easy real-time closing dates imposed via their actual surroundings, they have to warrantly to take action dependably, regardless of either actual faults (in undefined) and layout faults (in or software). A fault-tolerance method is vital for those promises to be commensurate with the protection and reliability standards of many lifestyles- and mission-critical purposes. This publication explains the motivations and the result of a collaborative project', whose target was once to seriously lessen the lifecycle charges of such fault tolerant platforms. The end-user businesses partaking during this venture already installation fault-tolerant platforms in serious railway, house and nuclear-propulsion purposes. besides the fact that, those are proprietary platforms whose architectures were adapted to satisfy domain-specific requisites. This has resulted in very expensive, rigid, and sometimes hardware-intensive strategies that, by the point they're constructed, confirmed and licensed to be used within the box, can already be out-of-date when it comes to their underlying and software program technology.
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Additional info for A Generic Fault-Tolerant Architecture for Real-Time Dependable Systems
1998] claim that is sufficient to use signatures only in the first round. Anyway, in our 2-round implementation of the algorithm, this leads to the same signature policy: sign the messages of the first round and do not sign the messages of the second round. We have taken into account this property in the protocol, but not (for clarity reasons) in the figures. 1 Practical Properties The protocol implements two rounds of message exchanges between three or four nodes. 4), we claim that: 10 11 • When n = 4, one arbitrary fault (at most) can be tolerated.
The formal approaches that have been applied include both theorem-proving and model-checking. 1 summarises the main features of the verifications carried out for each of the target mechanisms. 1- Formal Verification Approaches Target Mechanism Clock Synchronisation Interactive Consistency Fault Diagnosis Multi-level Integrity Properties Verified Agreement Accuracy Agreement Validity Correctness Completeness Segregation Policy (Multi-level Objects) Approach Theorem-Proving Model-Checking Description & Specification Higher Order Logic Process AI~ebra (CCS) and Tempera Logic (ACTL) Supporting Tool PVS JACK The work carried out on the verification of clock synchronisation relied heavily on PVS (Prototype Verification System) [Owre et al.
1) was derived as an instantiation of this general theory. The verifications concerning interactive consistency [Bernardeschi et al. 1998a], fault diagnosis [Bemardeschi et al. 1998b] and multi-level integrity [Semini 1998] were all based on model-checking using the JACK (Just Another Concurrency Kit) tool-set [Bouali et al. 1994]. This integrated environment provides a set of verification tools that can be used separately or in combination. Due to the complexity of the required models, the tool-set was extended to include a symbolic model checker for ACTL [Fantechi et al.
A Generic Fault-Tolerant Architecture for Real-Time Dependable Systems by David Powell